The present invention relates to solid state memory storage systems and devices. More particularly, the present invention provides methods and devices for enabling but hiding longer write-recovery times for weak memory cells and repairing a “bad memory cell” with a substitute cell for a memory device such as a dynamic random access memory (“DRAM”) device or others.
In solid state memory systems, a general class of memories includes low latency memories having effectively infinite endurance or usage-cycles and no degradation with respect to age or repeated accesses. Additional class of memories also includes relatively longer latency memories that do not have infinite endurance or usage cycles, and may degrade with respect to age or repeated accesses. In the case of the relatively long latency memories, sophisticated multi-error detection and correction algorithms have been implemented to correct for data cells that can degrade over the lifetime of memory devices due to aging effects or repeated accesses. In the case of low latency memories such as DRAM devices, however, effectively infinite endurance or usage-cycles are assumed so that once weak bits or bad bits are mapped out by device manufacturers, no errors should occur due to degradation of data cells due to aging effects or repeated accesses.
It is known that the conventional DRAM memory cell has an access transistor and a storage capacitor. The access transistor connects with the storage capacitor to a bitline when switched-on such that the capacitor stores the logic value placed on the bitline. Due to the tendency of a capacitor to lose its charge over time, DRAM memory cells must be periodically “refreshed”, which serves to maintain the value stored in each storage capacitor at its desired value. The amount of time that a cell can retain its logic value is referred to as its “data retention time”.
A trend in the development of memory cells is that the cell sizes have been shrinking due to advancements in process technology and the demand for ever larger memory capacity. This necessarily results in a reduction in the sizes of the access transistor and storage capacitor, which can lead to several limitations. For example, each access transistor exhibits leakage which acts to slowly drain stored charge from the storage capacitor. This leakage characteristic—and thus each cell's data retention time—varies from transistor to transistor; however, this variability increases as the size of the access transistors is reduced. Another problem is that a shrinking memory cell results in a smaller storage capacitor, and thus a reduced storage capacitance. This can also adversely affect the data retention time characteristics of the cells.
Moreover, the on-resistance (Ron) of the selection transistor may be higher-than-expected due to nature process variations, aging effects or repeated accesses. Consequently, a number of the memory storage cells may require longer-than-normal setting times such as longer tWR (Write Recovery) times. However, an increase in the cell storage (charging, or setting) times would decrease system performance. Consequently, techniques to hide the longer write recovery times are needed for weak memory cells.
Hence, it is highly desirable to develop a method of hiding longer write-recovery times for weak memory cells and repairing any “bad memory cell” with a substitute cell for a memory device.